module test_adder1;
reg a,b;
reg carry_in ;
wire sum;
wire carry_out;
adder1_behavorial A1(carry_out, sum, a, b, carry_in);
initial
begin
carry_in = 0; a = 0; b = 0;
# 100 if ( carry_out != 0 | sum !== 0)
$display("WRONG!");
else
$display("RIGHT!");
carry_in = 0; a = 0; b = 1;
# 100 if ( carry_out != 0 | sum !== 1)
$display("WRONG!");
else
$display("RIGHT!");
carry_in = 0; a = 1; b = 0;
# 100 if ( carry_out != 0 | sum !== 1)
$display("WRONG!");
else
$display("RIGHT!");
carry_in = 0; a = 1; b = 1;
# 100 if ( carry_out != 1 | sum !== 0)
$display("WRONG!");
else
$display("RIGHT!");
carry_in = 1; a = 0; b = 0;
# 100 if ( carry_out != 0 | sum !== 1)
$display("WRONG!");
else
$display("RIGHT!");
carry_in = 1; a = 0; b = 1;
# 100 if ( carry_out != 1 | sum !== 0)
$display("WRONG!");
else
$display("RIGHT!");
carry_in = 1; a = 1; b = 0;
# 100 if ( carry_out != 1 | sum !== 0)
$display("WRONG!");
else
$display("RIGHT!");
carry_in = 1; a = 1; b = 1;
# 100 if ( carry_out != 1 | sum !== 1)
$display("WRONG!");
else
$display("RIGHT!");
$finish;
end
endmodule
module adder1_behavorial (carry_out, sum, a, b, carry_in);
input a, b, carry_in;
output carry_out, sum;
assign sum = (~a&b&~carry_in)|(~carry_in&a&~b)|(a&b&carry_in)|(~a&~b&carry_in);
assign carry_out = a&carry_in|a&b|b&carry_in;
endmodule


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