2015.12.2(末)

module top;

wire A,B,C,D,F;
system_clock #1600 clock1(A);
system_clock #800 clock2(B);
system_clock #400 clock3(C);
system_clock #200 clock4(D);

not z1(a,A);
not z2(b,B);
not z3(c,C);
not z4(d,D);
and X1(F1,C,D);
and X2(F2,a,b,D);
and X3(F3,B,c,d);
and X4(F4,A,c,d);
or W(F,F1,F2,F3,F4);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>12800)$stop;

endmodule

2015.11.26 三位元行為模式

module fulladder (sum, c_out, a, b, c_in);
wire s1, c1, c2;
output sum;
output c_out;
input a, b, c_in;

assign{c_out,sum}=a+b+c_in;
endmodule

module adder3(sum, c_out, a, b, c_in);
wire [2:0] c;
output [2:0] sum;
output c_out;
input [2:0] a;
input [2:0] b;
input c_in;
fulladder fa1(sum[0], c[1], a[0], b[0], c_in) ;
fulladder fa2(sum[1], c[2], a[1], b[1], c[1]) ;
fulladder fa3(sum[2], c_out, a[2], b[2], c[2]) ;


endmodule

module main;
reg [2:0] a;
reg [2:0] b;
wire [2:0] sum;
wire c_out;

adder3 DUT (sum, c_out, a, b, 1'b0);

initial
begin
  a = 4'b0101;
  b = 4'b0000;
end

always #50 begin
  b=b+1;
  $monitor("%dns monitor: a=%d b=%d sum=%d", $stime, a, b, sum);
end

initial #2000 $finish;

endmodule

2015.11.18 結構模式

module top;
wire Cout, Sum, A, B, Cin;
system_clock #400 clock1(Cin);
system_clock #200 clock2(A);
system_clock #100 clock3(B);
adder1 M1(Cout, Sum, A, B, Cin);
endmodule

module adder1(Cout, Sum, A, B, Cin);
output Cout,Sum;
input A,B,Cin;
and I1 (AandB, A, B);
xor I2 (AxorB, A, B);
and I3 (And1, AxorB, Cin);
or I4 (Cout, AandB, And1);
xor I5 (Sum, AxorB, Cin);
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule

2015.11.18 一位元加法器 行為模式

module test_adder1;

 reg a,b;

 reg carry_in ; 

 wire sum;

 wire carry_out;

 adder1_behavorial A1(carry_out, sum, a, b, carry_in);

 initial 

  begin

    carry_in = 0; a = 0; b = 0; 

    # 100 if ( carry_out != 0 | sum !== 0) 

                $display("WRONG!");

              else

                $display("RIGHT!");

    carry_in = 0; a = 0; b = 1; 

    # 100 if ( carry_out != 0 | sum !== 1) 

               $display("WRONG!");

              else

               $display("RIGHT!");

    carry_in = 0; a = 1; b = 0; 

    # 100 if ( carry_out != 0 | sum !== 1) 

               $display("WRONG!");

              else

               $display("RIGHT!");

    carry_in = 0; a = 1; b = 1; 

    # 100 if ( carry_out != 1 | sum !== 0) 

               $display("WRONG!");

              else

               $display("RIGHT!");

    carry_in = 1; a = 0; b = 0; 

    # 100 if ( carry_out != 0 | sum !== 1) 

               $display("WRONG!");

              else

               $display("RIGHT!");

    carry_in = 1; a = 0; b = 1; 

    # 100 if ( carry_out != 1 | sum !== 0) 

               $display("WRONG!");

              else

               $display("RIGHT!");

    carry_in = 1; a = 1; b = 0; 

    # 100 if ( carry_out != 1 | sum !== 0) 

               $display("WRONG!");

              else

               $display("RIGHT!");

    carry_in = 1; a = 1; b = 1; 

    # 100 if ( carry_out != 1 | sum !== 1) 

               $display("WRONG!");

              else

               $display("RIGHT!");

    $finish;

  end

endmodule

module adder1_behavorial (carry_out, sum, a, b, carry_in);

 input a, b, carry_in;

 output carry_out, sum;

  assign sum = (~a&b&~carry_in)|(~carry_in&a&~b)|(a&b&carry_in)|(~a&~b&carry_in); 

  assign carry_out = a&carry_in|a&b|b&carry_in; 

endmodule

2015.11.26 結構模式

module fulladder (sum, c_out, a, b, c_in);

wire s1, c1, c2;

output sum;

output c_out;

input a, b, c_in;

xor g1(s1, a, b);

xor g2(sum, s1, c_in);

and g3(c1, a,b);

and g4(c2, s1, c_in) ;

xor g5(c_out, c2, c1) ;

endmodule

module adder3(sum, c_out, a, b, c_in);

wire [2:0] c;

output [2:0] sum;

output c_out;

input [2:0] a;

input [2:0] b;

input c_in;

fulladder fa1(sum[0], c[1], a[0], b[0], c_in) ;

fulladder fa2(sum[1], c[2], a[1], b[1], c[1]) ;

fulladder fa3(sum[2], c_out, a[2], b[2], c[2]) ;

endmodule

module main;

reg [2:0] a;

reg [2:0] b;

wire [2:0] sum;

wire c_out;

adder3 DUT (sum, c_out, a, b, 1'b0);

initial

begin

  a = 4'b0101;

  b = 4'b0000;

end

always #50 begin

  b=b+1;

  $monitor("%dns monitor: a=%d b=%d sum=%d", $stime, a, b, sum);

end

initial #2000 $finish;

endmodule

2015.11.4

                                                      module top;
  integer is;
  integer ia[1:0],ib[1:0];
  reg [1:0]a,b;
  reg s;
  wire [1:0]out;

  mux_behavioral mux2(out,a,b,s);

  initial
    begin
      for (is=0; is<=1; is = is + 1)
       begin
        s = is;
         for (ia[0]=0; ia[0]<=1; ia[0] = ia[0]+1)
          begin
           a[0]= ia[0];
            for (ia[1]=0; ia[1]<=1; ia[1] = ia[1]+ 1)
             begin
              a[1] = ia[1];
               for (ib[0]=0; ib[0]<=1; ib[0] = ib[0]+1)
                 begin
                   b[0] = ib[0];
                    for (ib[1]=0; ib[1]<=1; ib[1] = ib[1]+ 1)
                     begin
                      b[1] = ib[1];
                 #1 $display("a[0]=%d a[1]=%d b[0]=%d b[1]=%d s=%d out[0]%d out[1]%d",a[0],a[1],b[0],b[1],s,out[0],out[1]);
                      end
                    end
                  end
              end
         end
    end
endmodule

module mux_behavioral(OUT,A,B,SEL);
 output [1:0]OUT;
 input [1:0] A,B;
 input SEL;

mux1 X1(OUT[0],A[0],B[0],SEL);
mux1 X2(OUT[1],A[1],B[1],SEL);

endmodule

module mux1(OUT, A, B, SEL);
 output OUT;
 input A,B,SEL;

 not n1(NOT_SEL, SEL);
 and a1 (X, A, NOT_SEL);
 and a2 (Y, SEL, B);
 or  o1 (OUT, X, Y);

endmodule

四位元多工器

module top; 

wire A0,A1,A2,A3,SEL,B0,B1,B2,B3,out0,out1,out2,out3,a1out, a2out, n1out ,a3out ,a4out ,a5out ,a6out,a7out,a8out;

system_clock #100 clock1(A1); 

system_clock #200 clock2(A0); 

system_clock #6400 clock3(SEL);

system_clock #400 clock4(B1);

system_clock #800 clock5(B0);

system_clock #1600 clock6(A2); 

system_clock #3200 clock7(B2);

system_clock #800 clock8(A3); 

system_clock #6400 clock9(B3);

and a1(a1out, A1, SEL);

and a2(a2out, A0, SEL);

not n1(n1out, SEL);

and a3(a3out, B1, n1out);

and a4(a4out, B0, n1out);

and a5(a5out, A2, SEL);

and a6(a6out, B2, n1out);

and a7(a7out, A3, SEL);

and a8(a8out, B3, n1out);

or o1(out1, a1out,a3out);

or o2(out0, a2out,a4out);

or O3(out2, a5out,a6out);

or o4(out3, a7out,a8out);

endmodule 

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk; 

initial clk=0; 

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end 

always@(posedge clk)

 if($time>12800)$stop; 

endmodule