三位元多工器

module top; 

wire A0,A1,A2,SEL,B0,B1,B2,out0,out1,out2,a1out, a2out, n1out ,a3out ,a4out ,a5out ,a6out;

system_clock #100 clock1(A1); 

system_clock #200 clock2(A0); 

system_clock #6400 clock3(SEL);

system_clock #400 clock4(B1);

system_clock #800 clock5(B0);

system_clock #1600 clock6(A2); 

system_clock #3200 clock7(B2);

and a1(a1out, A1, SEL);

and a2(a2out, A0, SEL);

not n1(n1out, SEL);

and a3(a3out, B1, n1out);

and a4(a4out, B0, n1out);

and a5(a5out, A2, SEL);

and a6(a6out, B2, n1out);

or o1(out1, a1out,a3out);

or o2(out0, a2out,a4out);

or O3(out2, a5out,a6out);

endmodule 

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk; 

initial clk=0; 

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end 

always@(posedge clk)

 if($time>12800)$stop; 

endmodule