邏輯閘電路

module top; 

wire A, B, C, OUT1, OUT2;

system_clock #400 clock1(A); 

system_clock #200 clock2(B);

system_clock #100 clock3(C);

and a1(OUT1, A, B);

and al(OUT2, OUT1, C);

endmodule 

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk; 

initial clk=0; 

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end 

always@(posedge clk)

 if($time>1000)$stop; 

endmodule